Shift Register

ABSTRACT

A shift register includes a signal generating circuit for generating an output signal at an output end of the shift register in response to a clock signal while the signal generating circuit is turned on, a driving circuit electrically coupled to the signal generating circuit for controlling the signal generating circuit in response to an input signal received from an input end of the shift register, a primary reset circuit electrically coupled to the signal generating circuit for turning off the signal generating circuit and resetting the output signal from the output end, and a feedback circuit electrically coupled to the output end and the major reset circuit for controlling the primary reset circuit in response to the output signal and the clock signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a shift register, and more particularly, to a shift register capable of self-feedback.

2. Description of the Prior Art

A liquid crystal display (LCD) is a flat screen display panel that is manufactured from a glass base. A future trend of manufacturing an LCD will be by driving a control circuit that uses a thin film transistor (TFT) technology to make the glass base of the LCD whereas the current method of production utilizes an amorphous silicon layer that is far less suitable for producing high-grade transistors.

Please refer to FIG. 1 through to FIG. 3. FIG. 1 illustrates a diagram of a conventional LCD 100. FIG. 2 illustrates a diagram of a gate driving circuit 120 of the LCD 100 of FIG. 1. FIG. 3 illustrates a diagram of a shift register of the gate driving circuit 120 of FIG. 2. As illustrated in the figures, the LCD 100 includes a display array 110, and a gate driving circuit 120. The display array 110 is utilized for displaying images, and the gate driving circuit 120 is utilized for driving the display array 110. The gate driving circuit 120 includes a plurality of stage shift registers 122, the stage shift registers 122 are electrically coupled in a series connection and a gate signal GOUT is generated to drive the display array 110 in response to a first clock signal CK and a second clock signal XCK sequentially. The phase of the second clock signal XCK is opposite to the phase of the first clock signal CK. Regarding the connection of each stage shift register 122, the first clock signal CK and the second clock signal XCK alternately exchange information, which means that a clock signal input end CK1 and a clock signal input end CK2 is alternately coupled to the first clock signal CK and the second clock signal XCK. Each stage shift register 122 has an output end OUT, an input end IN, and a feedback end FB. The stage shift register 122 includes a signal generating circuit 310, a driving circuit 320, a primary reset circuit 330, and two secondary reset circuits 340, 350. As illustrated in FIG. 3, the signal generating circuit 310 is utilized for generating a gate signal GOUT(N) at the output end OUT of the shift register 122 in response to the first clock signal CK (which can also be the second clock signal XCK) while the signal generating circuit 310 is being turned on. The driving circuit 320 is utilized for controlling the signal generating circuit 310 in response to the input signal received by the input end IN of the shift register 122. The input signal received by the input end IN of the shift register 122 is the gate signal GOUT(N−1) from a previous stage shift register. The primary reset circuit 330 is utilized for turning off the signal generating circuit 310 and resetting the gate signal GOUT(N) from the output end OUT (which means that voltage of the output end is being lowered to a predetermined low electrical potential VSS), and feedback signal transmitted by the feedback end FB is a gate signal GOUT(N+1) from an output end of a previous stage shift register. The secondary reset circuits 340, 350 are utilized for alternately turning off the signal generating circuit 310 and resetting the output signal of the output end OUT in response to the first clock signal CK and the second clock signal XCK.

Although the functions of the secondary reset circuits 340, 350 and the primary reset circuit 330 are quite similar, the primary reset circuit 330 differs from the secondary reset circuits 340, 350 in that it only operates after receiving a gate signal GOUT(N+1) from a next stage shift register. The secondary reset circuits 340, 350 operate continuously for long period of time. When the TFT is in operation for a long period of time, then efficient can reduced as well as its lifespan. Therefore, the primary reset circuit 330 is only operated once every operation cycle, thus noise interference can be prevented thereby prolonging the operation lifespan of the product.

To further explain the operation of the conventional shift register 122 in detail, please refer to FIG. 4 and at the same time to FIG. 3. FIG. 4 illustrates a clock diagram of each related signal of the shift register 122 of FIG. 3 during operation. As illustrated in FIG. 4, in time T1, the input signal (which can be the gate signal GOUT(N−1) or a start signal (ST) from the output end of the previous stage shift register) is being raised to a high electrical potential, hence thin film transistor (TFT) TFT₁ of the driving circuit 320 is initialized, which causes the signal generating circuit 310 to initialize as well. However, the first clock signal CK at T1 is at low electrical potential, the gate signal GOUT(N) from the output end OUT remains in a low electrical potential, furthermore because the feedback signal GOUT (N+1) of the feedback end FB is at low electrical potential the primary reset circuit 330 does not operate at point N₄ because electrical potential is low, because the first clock signal CK is at low electrical potential the secondary reset circuit 340 does not operate at point N₂ because electrical potential is low, and because the input signal GOUT(N−1) or ST turns on TFT₈ at T1 the secondary reset circuit 350 does not operate at point N₃ because electrical potential is low.

At time T2, the input signal GOUT(N−1) or ST received by the input end IN is being lowered to low electrical potential, thus TFT₁ of the driving circuit 320 is turned off, however the signal generating circuit 310 is still turned on, electrical potential is raised to high electrical potential at N₁ due to electric capacitance on the first clock signal CK when the first clock signal CK is raised to high electrical potential, and the gate signal GOUT(N) from the output end OUT also becomes high electrical potential. Furthermore, because TFT₁₅ is turned on by the first clock signal CK at T2 the primary reset circuit 330 does not operate at point N₄ because electrical potential is low, because TFT₁₁ is turned on by the gate signal GOUT(N) from the output end OUT at T2 the secondary reset circuit 340 does not operate at point N₂ because electrical potential is low, and because the second clock signal XCK is at low electrical potential the secondary reset circuit 350 does not operate at point N₃ because electrical potential is low.

At time T3, the primary reset circuit 330 turns on TFT₁₆, TFT 17, and turns off the signal generating circuit 310 (N1 is at low electrical potential) and lowers the gate signal GOUT(N) from the output end OUT into low electrical potential, because the second clock signal XCK turns on TFT₁₄ and the feedback signal GOUT(N+1) of the feedback end FB rises to high electrical potential which directly causes point N₄ to be high electrical potential. Furthermore, because the first clock signal CK is at low electrical potential the secondary reset circuit 340 does not operate at point N₂ because electrical potential is low, however because the second clock signal XCK is at high electrical potential the secondary reset circuit 350 at point N₃ is at high electrical potential) and at the same time TFT₃, TFT₆ are being turned on, the signal generating circuit 310 is being turned off, and the gate signal GOUT(N) from the output end OUT is being lowered to low electrical potential.

Within other following time, the secondary reset circuit 340 and the secondary reset circuit 350 will operate alternately to turn off the signal generating circuit 310 and lower the gate signal GOUT(N) from the output end to low electrical potential until the input signal GOUT(N−1) of the input end IN or ST is again raised to high electrical potential. Also, a next stage shift register 122 will repeat the above-mentioned actions, thus the gate signal GOUT can be sequentially generated to drive the display array 10.

However, the gate signal GOUT from each stage shift register 122 is not only utilized for driving the display array, but also utilized for outputting to an input end IN of a next stage shift register 122 and a feedback end FB of a previous stage shift register 122, therefore the work load of the output end OUT is increased. This action also results in increasing the rising time and falling time of the gate signal GOUT from each stage shift register 122. Furthermore, a feedback end FB of a last stage shift register of the gate driving circuit 120 is unable to receive a feedback signal thus causing a primary reset circuit 330 of the last state shift circuit 122 to stop operating, which results in shortening of the operation life span of the last stage shift register 122 that can cause damage on the gate driving circuit 120.

SUMMARY OF THE INVENTION

The claimed invention discloses a shift register. The shift register comprises an output end; an input end; a signal generating circuit for generating an output signal at the output end in response to a clock signal while the signal generating circuit is turned on, a driving circuit electrically coupled to the signal generating circuit for controlling the signal generating circuit in response to an input signal from the input end, a primary reset circuit electrically coupled to the signal generating circuit for turning off the signal generating circuit and resetting an output signal from the output end, and a feedback circuit electrically coupled to the output end and the primary reset circuit for controlling the primary reset circuit in response to the output signal and the clock signal.

The claimed invention further discloses a thin film transistor (TFT) liquid crystal display (LCD). The LCD comprises a display array; and a gate driving circuit, having a plurality of stage shift registers coupled in a series, electrically connected to the display array. Each stage shift register comprises an output end; an input end; a signal generating circuit for generating an output signal at the output end of the shift register while the signal generating circuit is turned on in response to a clock signal; a driving circuit, electrically coupled to the signal generating circuit for controlling the signal generating circuit in response to an input signal from the input end; a primary reset circuit, electrically coupled to the signal generating circuit for turning off the signal generating circuit and resetting an output signal from the output end; and a feedback circuit, electrically coupled to the output end and the primary reset circuit for controlling the primary reset circuit in response to the output signal and the clock signal.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a diagram of a conventional liquid crystal display (LCD).

FIG. 2 illustrates a diagram of a gate driving circuit of the LCD of FIG. 1.

FIG. 3 illustrates a diagram of a shift register of the gate driving circuit of FIG. 2.

FIG. 4 illustrates a clock diagram of each related signal during operation of the shift register of FIG. 3.

FIG. 5 illustrates a diagram of an LCD according to the present invention.

FIG. 6 illustrates a diagram of a gate driving circuit of the LCD of FIG. 5.

FIG. 7 illustrates a shift register of the gate driving circuit of FIG. 6.

FIG. 8 illustrates a clock diagram of each related signal during operation of the shift register of FIG. 7.

DETAILED DESCRIPTION

Please refer to FIG. 5 through to FIG. 7. FIG. 5 illustrates a diagram of an LCD 500 according to the present invention. FIG. 6 illustrates a diagram of a gate driving circuit 520 of the LCD 500 of FIG. 5. FIG. 7 illustrates a shift register of the gate driving circuit 520 of FIG. 6. The LCD 500 of the present invention includes a display array 510, and a gate driving circuit 520. The display array 510 is utilized for displaying images, and the gate driving circuit 520 is utilized for driving the display array 510. The gate driving circuit 520 includes a plurality of stage shift registers 522 coupled in series. And gate signals GOUT are generated by the plurality of stage shift registers 522 to drive the display array 510 in response to a first clock signal CK and a second clock signal XCK sequentially. Phase of the second clock signal XCK inter-compensates phase of the first clock signal CK. Regarding the connection of each stage shift register 522, the first clock signal CK and the second clock signal XCK alternately exchanges information, which means that a clock signal input end CK1 and a clock signal input end CK2 are alternately coupled to the first clock signal CK and the second clock signal XCK. The difference with the prior art is that in the present invention, each stage shift register 522 has an input end IN and an output end OUT, and without a feedback end FB. Each shift register 522 further includes a signal generating circuit 710, a driving circuit 720, a primary reset circuit 730, a feedback circuit 760, and two secondary reset circuits 740, 750. As illustrated in FIG. 7, the signal generating circuit 310 is utilized for generating a gate signal GOUT(N) at the output end OUT of the shift register in response to the first clock signal CK (which can also be the second clock signal XCK) while the signal generating circuit 310 is turned on. The driving circuit 320 is utilized for generating a driving signal Q(N) to control the signal generating circuit 310 in response to the input signal from the input end IN of the shift register 122. As illustrated in FIG. 7, the signal generating circuit 710 is utilized for generating a gate signal GOUT(N) at the output end OUT of the shift register 522 in response to the first clock signal CK (which can also be the second clock signal XCK) while the signal generating circuit 710 is turned on. The driving circuit 720 is utilized for controlling the signal generating circuit 710 in response to the input signal from the input end IN of the shift register 522. The input signal from the input end IN of the shift register 522 is a start signal (ST) or a gate signal GOUT(N−1) from a previous stage shift register. The primary reset circuit 730 is utilized for turning off the signal generating circuit 710 and resetting the gate signal GOUT(N) from the output end OUT (which means that voltage of the output end is being lowered to a predetermined low potential VSS). The feedback circuit 760 is utilized for generating a feedback signal to control operation of the primary reset circuit 730 at point N₁₄ in response to the gate signal GOUT(N), the first clock signal CK and the second clock signal XCK. For example, TFT₆₆ of the feedback circuit 760 is utilized for generating a feedback signal in response to the second signal XCK at point N14 while the TFT₆₆ is turned on, and TFT₆₄ of the feedback circuit 760 is utilized for controlling on and off of the TFT₆₆ in response to the gate signal GOUT(N). Furthermore, TFT₆₇ and TFT₆₈ are respectively utilized for resetting the feedback signal in response to the gate signal GOUT(N) and the first clock signal CK, and TFT₆₅ of the feedback circuit 760 is the signal for resetting of the TFT₆₄ output end in response to voltage at point N₁₂. The secondary reset circuits 740, 750 are utilized for alternately turning off the signal generating circuit 710 and resetting the gate signal GOUT(N) from the output end OUT.

The feedback circuit 760 of each stage shift register 522 can generate a feedback signal to replace a gate signal GOUT (N+1) from the output end of a next shift register, which also means that the primary reset circuit 730 can turn off the signal generating circuit 710 and reset the gate signal GOUT(N) from the output end OUT in response to the feedback signal generated by the feedback signal 760, therefore it is not required that the output end OUT of the shift register be coupled to a feedback end of a previous shift register.

To further explain the detailed operation of the shift register 522, please refer to FIG. 7 and FIG. 8 at the same time. FIG. 8 illustrates a clock diagram of each related signal during operation of the shift register 522 of FIG. 7. As illustrated in FIG. 8, in time T1, the input signal received by the input end IN (which can be the gate signal GOUT(N−1) or a start signal (ST) from the output end of a previous stage shift register) is being raised to a high electrical potential, hence TFT₅₁ of the driving circuit 720 is initialized as well as the signal generating circuit 710. However, the first clock signal CK at T1 is at low electrical potential, the gate signal GOUT(N) from the output end OUT remains at low electrical potential, the feedback circuit 760 is unable to initialize TFT₆₄ because the feedback signal GOUT (N+1) is at low electrical potential, which causes point N₁₅ to be low electrical potential, and the primary reset circuit 730 does not operate at point N₁₄ because electrical potential is low (which means that the feedback signal of the feedback circuit 760 is at low electrical potential), furthermore, the secondary reset circuit 740 does not operate at N₁₂ as electrical potential is low (which means that the first clock signal CK is at low potential), and because the input signal GOUT(N−1) or ST turns on TFT₅₈ at T1, the secondary reset circuit 750 does not operate at point N₁₃ as electrical potential is low.

At time T2, the input signal GOUT(N−1) or ST received by the input end IN is being lowered to low electrical potential, in doing so, TFT₁₅ of the driving circuit 720 is turned off, however, the signal generating circuit 710 is still turned on and electrical potential is raised to high electrical potential at N₁₁ due to electric capacitance on the first clock signal CK when the first clock signal CK is raised to high electrical potential. Additionally, at this time, the gate signal GOUT(N) from the output end OUT becomes high electrical potential, the feedback circuit 760 turns on TFT₆₄ because the gate signal GOUT(N) from the output end is at high electrical potential, therefore point N15 becomes high potential as well, and the primary reset circuit 730 does not operate at point N₁₄ because electrical potential is low, furthermore, because the gate signal GOUT(N) from the output end turns on TFT₆₁ at T2 the secondary reset circuit 740 does not operate at N₁₂ because electrical potential is low, and because the second clock signal XCK is at low potential the secondary reset circuit 750 does not operate at point N₁₃ because electrical potential is low.

At time T3, the second clock signal XCK is at high electrical potential, which directly causes point N₁₄ to rise to high electrical potential (which means that the feedback signal of the feedback circuit 760 is also at high electrical potential), point N₁₅ is raised to high electrical potential due to electric capacitance on the second clock signal XCK when the second clock signal XCK is raised to high electrical potential. The primary reset circuit 730 turns on TFT₆₉, TFT₇₀ because point N14 is at high electrical potential, which also means that the signal generating circuit 710 (point N11 is lowered to low electrical potential) is turned off and the gate signal GOUT(N) from the output end OUT is lowered to low electrical potential. Furthermore, because the first clock signal CK is at low electrical potential the secondary reset circuit 740 does not operate because point N₁₂ is at low electrical potential, but the secondary reset circuit 750 simultaneously turns on TFT₅₂, TFT₅₆ because point N₁₃ is at high electrical potential and turns off the signal generating circuit 710, and the gate signal GOUT(N) from the output end OUT is being lowered to low electrical potential.

At time T4, because N₁₂ is being raised to high electrical potential, point N₁₅ is being lowered to low electrical potential because TFT₆₅ is turned on, and because the first clock signal CK turns on TFT₆₈ at T4 the primary reset circuit 730 does not operate because point N₁₄ is being lowered to low electrical potential). Furthermore, after T3, the secondary reset circuit 740 and the secondary reset circuit 750 will alternately turn off the signal generating circuit 710 and lower the gate signal GOUT(N) from the output end to low electrical potential. Also, a next stage shift register 522 will also repeat the above-mentioned thereby sequentially generating the gate signal GOUT (which is also the output signal) to drive the display array 510.

In conclusion, the shift register 522 includes a feedback circuit 760 capable of self-feedback such that the primary reset circuit 730 can turn off the signal generating circuit 710 and reset the output signal (gate signal GOUT) in response the feedback signal generated from the feedback circuit 760.

In comparison to the prior art, it is not required that the output end OUT of the shift register 522 of the present invention be coupled to a feedback end of a previous shift register, thus workload of the output end OUT of each shift register 522 can be reduced so as to reduce rising time and falling time of the gate signal GOUT. Furthermore, a feedback end FB of a last stage shift register 522 of the gate driving circuit 520 is able to receive a feedback signal, therefore damage to the last stage shift register 522 or even the gate driving circuit 520 can be prevented.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. 

1. A shift register, comprising: an output end; an input end; a signal generating circuit for generating an output signal at the output end in response to a clock signal while the signal generating circuit is turned on; a driving circuit, electrically coupled to the signal generating circuit, for controlling the signal generating circuit in response to an input signal from the input end; a primary reset circuit, electrically coupled to the signal generating circuit, for turning off the signal generating circuit and resetting an output signal from the output end; and a feedback circuit, electrically coupled to the output end and the primary reset circuit, for controlling the primary reset circuit in response to the output signal and the clock signal.
 2. The shift register of claim 1, further comprising a secondary reset circuit, electrically coupled to the output end and the signal generating circuit, for turning off the signal generating circuit and resetting the output signal from the output end in response to the clock signal.
 3. The shift register of claim 1, wherein the input end is electrically coupled to an output end of a previous stage shift register.
 4. The shift register of claim 1, wherein the feedback circuit comprises: a first thin film transistor (TFT) for outputting a feedback signal in response to the clock signal while the first TFT is turned on; a second TFT for controlling the first TFT in response to the output signal from the output end; a third TFT for resetting the feedback signal from the first TFT in response to the clock signal; a fourth TFT for resetting the feedback signal from the first TFT in response to the output signal from the output end; and a fifth TFT for resetting the signal from the second TFT while the fifth TFT is turned on.
 5. The shift register of claim 4, wherein the primary reset circuit comprises: a sixth TFT for turning off the signal generating circuit while the sixth TFT is turned on by the feedback signal from the first TFT; and a seventh TFT for resetting the output signal from the output end while the seventh TFT is turned on by the feedback signal from the first TFT.
 6. A thin film transistor (TFT) liquid crystal display (LCD), comprising: a display array; and a gate driving circuit, having a plurality of stage shift registers coupled in a series, electrically connected to the display array, each stage shift register comprising: an output end; an input end; a signal generating circuit for generating an output signal at the output end of the shift register while the signal generating circuit is turned on in response to a clock signal; a driving circuit, electrically coupled to the signal generating circuit for controlling the signal generating circuit in response to an input signal from the input end; a primary reset circuit, electrically coupled to the signal generating circuit for turning off the signal generating circuit and resetting an output signal from the output end; and a feedback circuit, electrically coupled to the output end and the primary reset circuit for controlling the primary reset circuit in response to the output signal and the clock signal.
 7. The LCD of claim 6, wherein the shift register further comprises a secondary reset circuit, electrically coupled to the output end and the signal generating circuit for turning off the signal generating circuit and resetting the output signal from the output end in response to the clock signal.
 8. The LCD of claim 6, wherein the input end is, electrically coupled to an output end of a previous shift register.
 9. The LCD of claim 6, wherein the feedback circuit comprises: a first thin film transistor (TFT) for outputting a feedback signal while the first TFT is turned in response to the clock signal; a second TFT for controlling the first TFT in response to the output signal from the output end of the shift register; a third TFT for resetting the feedback signal from the first TFT in response to the clock signal; a fourth TFT for resetting the feedback signal from the first TFT in response to the output signal from the output end; and a fifth TFT for resetting the signal from the second TFT while the fifth TFT is turned on.
 10. The LCD of claim 9, wherein the primary reset circuit comprises: a sixth TFT for turning off the signal generating circuit while the sixth TFT is turned on by the feedback signal from the first TFT; and a seventh TFT for resetting the output signal from the output end while the seventh TFT is turned on by the feedback signal from the first TFT. 